1. Field of the Invention
This invention relates to a method of manufacturing a bipolar transistor and, more particularly, to a manufacturing method for such a bipolar transistor that has an emitter region and an external or graft base region formed in a self alignment manner.
2. Description of the Related Art
A bipolar transistor can be enhanced in device performances such as a current gain and a response speed by forming the external base region at a precise position with respect to the emitter region. For this purpose, such a method has been proposed that forms the emitter region and the external base region in a self alignment manner with each other. This method will be described below with reference to FIG. 6A to FIG. 6D.
In a step of FIG. 6A, a field oxide film 47 is selectively formed on a collector region 44 by using a selectively oxidizing method. The portion of the collector region 44 which is not covered with the oxide film 47 define a base formation portion.
In a step of FIG. 6B, a polysilicon film 50 is formed on the entire surface and then boron ions are implanted to the polysilicon film 50. Thereafter, an oxide film 51 is formed on the polysilicon film 50.
In a step of FIG. 6C, the oxide film 51 and the polysilicon film 50 are etched in that order by an anisotropic etching technique to form an opening section 80, thereby exposing a part of the collector region 44.
In a step of FIG. 6D, boron ions are injected to the exposed part of the collector region 44 to form an intrinsic or active base region 48. A side wall made of silicon oxide 55 is then formed on a side surface of the polysilicon film 50 that forms the opening section 80. A polycrystalline layer doped with arsenic is thereafter deposited over the entire surface, followed by patterning to form a polysilicon emitter electrode 61. A thermal treatment is then conducted to have arsenic diffuse from the emitter electrode 61 into the base region 48 to form an emitter region 56. Simultaneously with this heat treatment, boron is diffused from the polysilicon layer 50 into the collector region 44 to thereby form an external or graft base region 60. Thus, the external base region 60 is formed in a self alignment manner with the emitter region 56.
However, in the method as described above, a surface portion of the collector region 44 is considerably etched away in the step of forming the opening section 80, as shown in FIG. 6C. This is because the polysilicon film 50 varies in thickness and hence a relatively excessive etching is required to completely expose the part of the collector region 44. For this reason, the base region 48 is in slight contact with the external base region 60, as shown in FIG. 6D, resulting in increase in a base resistance which deteriorates the high frequency performance. In the worst case, the base region 48 has no contact with the external base region 60. In addition, the surface portion of the collector region 44 is exposed or subjected directly to the anisotropic etching, in the step of FIG. 6C, and hence the base and emitter regions 48 and 56 formed thereat has many crystal defects, which increases leakage current.
In order to avoid the above problems, therefore, such a method that employs an oxide film as an etching stop film is disclosed in Japanese Laid-open Patent Application No. Sho 63-214663. This method is applied to produce the so-called Bi-CMOS device including a bipolar transistor and complementary MOS transistor and will be described below with reference to FIGS. 7A to 7D.
In a step of FIG. 7A, in a bipolar region 100 where bipolar transistor is to be fabricated, an N.sup.+ type buried layer 42 is embedded or buried between a part of a P type silicon substrate 41 and an N.sup.- type epitaxial layer 44. In an NMOS region 200 where an N channel MOS transistor is to be fabricated, a P.sup.+ type buried region 43 is formed between the silicon substrate 41 and a P well 45. In a PMOS region 300 where a P channel MOS transistor is to be fabricated, an N.sup.+ type buried region 42 is formed between the substrate 41 and an N well 46, a field oxide film 47 is thereafter formed in the epitaxial layer 44, the P well 45, and the N well 46 using the selective oxidizing method to define the respective active regions of the PMOS region 300, the NMOS region 200, and the bipolar transistor region 100. In the bipolar region 100, thereafter, a P type intrinsic base region 48 is formed by selective-implantation of boron ions. Subsequently, silicon oxide films 49 is formed on the respective active regions. The films 49 serve as gate insulating films for MOS transistors.
In a step of FIG. 7B, the silicon oxide film 49 on the intrinsic base region 48 is selectively removed with a photolithography to form an opening section 49A for an external base contact. A P type polycrystalline silicon film 50 and a silicon dioxide film 51 are then sequentially formed on an entire surface. The polysilicon film 50 is doped with P-type impurities.
In a step of FIG. 7C, the silicon dioxide film 51 and the polycrystalline film 50 are selectively etched by the photolithography to form a base electrode 54, which is contact with the P type intrinsic base region 48 through the opening section 49A, and gate electrodes 52 and 53 for N-channel and P-channel MOS transistors. A silicon dioxide film is then formed on an entire surface, followed by the so-called etch-back to form side walls 55 on the respective side surfaces of the base electrode 54 and the gate electrodes 52 and 53. In this etch-back process, the portions of the silicon dioxide film 49 are also removed, as shown to expose respective parts of the P type intrinsic base region 48, the N.sup.- type epitaxial layer 44, the P well 45, and the N well 46. In particular, a hole 90 defines an emitter region. Thereafter, N type impurities such as arsenic (As) are selectively implanted to form an emitter region 56, a collector contact region 57 and source and drain regions 58 of the N channel MOS transistor. Subsequently, P type impurities such as boron (B) are selectively implanted to form source and drain regions 59 of the P channel MOS transistor. During the annealing processes for activating the implanted impurities, the P type impurities included in the base region 54 are diffused into the P type intrinsic base region 48 through the opening section 49A to thereby form a P.sup.+ type external base region 60.
In a step of FIG. 7D, an N-type polycrystalline silicon layer is formed, followed by being patterned to form an emitter electrode 61.
In the bipolar transistor manufactured by the foregoing method, the silicon oxide film 49 serves as an etching stop for the collector 44 upon etching the polysilicon layer 50. Accordingly, the problems as discussed in the method of FIG. 6 are solved.
However, as is apparent from FIGS. 7B and 7C, the hole 49A for forming the external base region 60 and the hole 70 for forming the emitter region 56 are provided in separate steps from each other. For this reason, the distance between the external base region 60 and the emitter region 56 is affected by the respective photolithography processes and thus deviated from the designed value. In other words, the external base region 60 and the emitter region 56 are not formed in a self-aligned manner. The bipolar transistor is thus inferior in electrical characteristics to that shown in FIG. 6.